State, Timing, and Why Hardware Bugs Are Subtle

Why Timing Matters

Correct logic can still fail if timing assumptions are wrong.

Cycle n   →   Cycle n+1
 State         State

Control vs Data Path

Design separates control logic from data movement.

 Control (FSM)
      ↓
  Data Path

Software Lessons

Hardware teaches explicit state, timing discipline, and clear ownership.

Takeaway

Correctness includes time.